1. Field of the Invention
The present invention relates to a path test signal generator and a path test signal checker for use in a digital transmission system and a synchronous transmission system, and more specifically to a path test signal generator and a path test signal checker for use in a digital transmission system and a synchronous transmission system preferably applied to a network such as B-ISDN (Broadband Integrated Services Digital Network) or SONET (Synchronous Optical NETwork).
2. Description of the Background Art
Recently, digital networks having fast and large transmission capacity, such as B-ISDN or SONET, have been developed and put into practice as the transmission capacity increases and the standardization of interfaces is internationally promoted with the development of digital telecommunications techniques. With fundamental technology supporting such digital networks, synchronous digital hierarchy standardizing the network node interface in general aspects of digital transmission systems are being promulgated, such as ITU-T (International Telecommunications Union-Telecommunications standardization sector) draft Recommendation G.707 (July, 1995).
The synchronous digital hierarchy, adopting transmission frames with a rate of 155.52 Mbps, that is, so-called synchronous transport module level-1 (STM-1) frames as basic interface, is a synchronous multiplexing scheme that multiplexes primary to quaternary group rate information different from nation to nation into frames with a rate of internationally standardized one. More specifically, four or three pieces of the primary group rate information with a rate of 1.5 Mbps or 2 Mbps are multiplexed to the secondary group information with a rate of 6 Mbps. Seven or 21 pieces of the secondory group rate information are multiplexed to the tertiary group rate information with a rate of 50 Mbps or to the quaternary rate information with a rate of 150 Mbps. Three pieces of the tertiary group rate information are multiplexed and provided with a header of a certain format, and are assembled into a transmission frame with a format according to the synchronous transport module STM-1. On the other hand, the 150 Mbps quaternary group rate information is provided with a header and accommodated into a transmission frame of the synchronous transport module STM-1.
The synchronous transport module STM-1 has a header with 9 rows by 9 columns in terms of bytes, and a payload with 9 rows by 261 columns in terms of bytes for accommodating information, thus having 9 rows by 270 columns. The header includes in the first to third rows a regenerator section overhead (RSOH) representing management information about a regenerator section, in the fourth row an AU (Administrative Unit) pointer which indicates the start point of the payload and aligns an asynchronism, and in the fifth to ninth rows a multiplex section overhead (MSOH) for representing management information on multiple sections.
In the quaternary group rate, the information accommodated in the payload of the synchronous transport module STM-1 consists of a path overhead (POH) in the first row, and substantial information accommodated in the remaining 260 columns. On the other hand, in the tertiary group rate, the information consists of three blocks of information, each block including 87 columns of information with the path overhead placed in the first row. The columns are each byte-interleaved to form the 261-column payload in the STM-1. In the foregoing cases, the payloads including path overheads POHs are called virtual containers VC-3 and VC-4, and the substantial information portions excluding the path overheads POHs are referred to as containers C-3 and C-4, respectively. In addition, the virtual containers VC-3 and VC-4 plus the AU pointers are called administrative units AU-3 and AU-4, respectively.
Likewise, in the primary and secondary groups, portions including only substantial information are called containers C11, C-12 and C-2 in ascending order of the rate, and those portions plus the headers are referred to as virtual containers VC-11, VC-12 and VC-2. Furthermore, the virtual containers plus TU (tributary unit) pointers similar to the AU pointers are called tributary units TU-11, TU-12 and TU-2. Those tributary units which are multiplexed after byte-interleaving are called tributary unit groups TUG-2 and TUG-3. The tributary unit groups TUG-2 and TUG-3, when multiplexed in such a manner that they are byte-interleaved and provided with path overheads POHS, constitute virtual containers VC-3 and VC-4, respectively.
The synchronous transport module STM-1 is bit-serially read in the row direction from the first bit in the first column to the final bit in the ninth row, and transmitted over a channel in 125 microseconds, thereby forming a transmitted frame with a rate of 155.52 Mbps. In a transmission system based on the synchronous digital hierarchy, each node, that is, each transmission equipment performs its transmission using transmission frames based on the synchronous transmission module STM-1, and in particular in a large capacity channel, it carries out its transmission using transmission frames based on synchronous transport module STM-N formed by byte-interleaving the synchronous transport module STM-1, where N is the n-th power of two, and n is an even integer including zero. The synchronous transport module STM-N includes a 9-row by (9.times.N)-column section overhead SOH and a 9-row by (261.times.N)-column payload, and has a standardized transmission rate of 620 Mbps when N=4, 1.8 Gbps when N=12 (applied only to submarine cables), 2.4 Gbps when N=16, and 9.9 Gbps when N=64. Thus, the transmission rate takes a value of integer multiple N of the basic interface.
As a path test method for such a digital transmission system, digital test patterns are defined in CCITT (The International Telegraph and Telephone Consultative Committee, now called ITU-T) Recommendation 0.150 (1992.10) for the tests of the digital transmission equipment with various transmission rates. For example, a 15th order PN (pseudo-random) test patterns are assigned to the test at 1.5 Mbps, 2 Mbps, 6 Mbps, 8 Mbps, 32 Mbps and 44 Mbps. The 15th order PN pattern is an M (maximum length) sequence pattern with a length of (2.sup.15 -1)=32,767 bits, which is generated by a 15-stage shift register whose 14th and 15th stage outputs are added in a modulo-two addition stage, and the result is fed back to the input of the first stage of the shift register. In this case, a maximum of 15 consecutive 1's can appear.
Besides, the 23rd order PN patterns are as signed to the tests at the rate of 34 Mbps and 139 Mbps. The 23rd order PN pattern is an M sequence pattern with a length of (2.sup.23 -1)=8,388,607 bits, which is generated by a 23-stage shift register whose 18th and 23rd stage outputs are added in a modulo-two stage, and the result is fed back to the first stage of the shift register. In this case, a maximum of 23 consecutive 1's can appear.
In the foregoing cases, rate sequences of the existing hierarchy are also included: In the synchronous digital hierarchy, the 15th order PN patterns are assigned to the 1.5 Mbps container C-11, 2.0 Mbps container C-12, 6 Mbps container C-2, and 44 Mbps container C-3, and the 23rd order PN patterns are assigned to the 34 Mbps container C-3 and 139 Mbps container C-4. As an example applying such PN patterns, ITU Recommendation O.SDH Annex 3 (October, 1993) defines a test signal structure of the synchronous digital hierarchy.
This document discloses a test signal structure, in which the 23rd order PRBS (Pseudo Random Binary Sequence) test pattern according to Recommendation 0.150 is inserted into the containers C-3 and C-4 except for the section overhead SOH and path overhead POH of the synchronous transport module. Likewise, test signal structures are disclosed, in which the PRBS test patterns according to Recommendation 0.150 are inserted into the containers C-11, C12 and C-2 which are multiplexed to the synchronous transport module. In addition, test signal structures are disclosed, in which the 23rd PRBS test patterns according to Recommendation 0.150 are inserted into all the STM-N frame bytes except for the regenerator section overhead RSOH of the synchronous transport module.
As a circuit for checking such PN patterns, PN pattern detectors are disclosed in Japanese patent laid-open publication No. 2-140031 (1990), Japanese patent publication No. 7-118697 (1995) and Japanese patent laid-open publication No. 4-4631 (1992).
The first publication, No. 2-140031 (1990), discloses a PN pattern detector which comprises a shift register for shifting an input pattern, a PN pattern generator for generating a PN pattern, a comparator for comparing their outputs, and a detector for detecting a maximum consecutive 0's of the PN pattern, and which shortens the acquisition time for pulling into synchronism by shifting the value of the shift register on the detected result, thereby carrying out error detection by comparing the acquisition patterns by the comparator. It is one of the serial self-synchronous PN pattern checkers which independently establishes synchronization at a receiving side without synchronizing with a transmitting side.
The second publication, No. 7-118697 (1995), discloses a serial self-synchronous PN pattern checker as in the first document. It includes a first n-stage shift register for shifting an input pattern, a PN pattern generator including a second n-stage shift register for generating a PN pattern, and a comparator for comparing those PN patterns, wherein one of n 2-1 selectors is connected to each input of the second n-stage shift register in the PN pattern generator for selecting either the output of its preceding stage or the output of the corresponding stage of the first n-stage shift register so that the first n-stage shift register is pulled in independently of the PN pattern generator, and the values of the first n-stage shift register are fed to the second n-stage shift register in a single clock in the pulled-in state, thereby making error detection by comparing their outputs.
The third publication, No. 4-4631 (1992), discloses a parallel self-synchronous PN pattern checker including a serial-to-parallel converter for converting a serial input pattern into a parallel pattern, a PN pattern generator for generating a PN pattern, a converter for converting its output, a comparator for comparing its output with the input pattern converted into parallel form, and a decision circuit for deciding the establishment of the synchronization.
The foregoing prior art references, however, disclose only common generation and detection of the PN pattern, but do not disclose a system that can implement the path test in the digital transmission system to which the synchronous digital hierarchy is applied. For example, it is necessary to contrive an insertion method of the PN pattern into the individual container C of the synchronous transport module according to ITU Recommendation O.SDH Annex 3, a detection method thereof, and a circuit configuration for implementing these methods.
In particular, although ITU Recommendation O.SDH Annex 3 discloses up to the test signal structure of the containers C-11, C-12, C-2, C-3 and C-4, it remains a future task to construct the test signal in the transmission frame including container C-4-Xc formed by linking the container C-4, where Xc is the n-th power of 2, and n is an even number including zero. Moreover, Recommendation 0.150 defines only the test patterns at a rate of 139 Mbps corresponding to the container C-4, without disclosing any test patterns corresponding to the container C-4-Xc faster than the container C-4.
This presents a further problem in that although a circuit for generating and detecting the test patterns for the container C-4-Xc is developed and applied to the transmission equipment, the equipment will become bulky and expensive because the circuit operating at a rate of several times 150 Mbps is difficult to implement using the state of the art LSI technology.